Dr. Mahdi Taheri

An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

MJ Sekonji, A Mahani, M Mirsadeghi, M Taheri

arXiv preprint arXiv:2603.18054, 2026

DART: Input-Difficulty-AwaRe Adaptive Threshold for Early-Exit DNNs

P Patne, M Taheri, C Herglotz, M Jenihhin, M Krstic, M Hübner

arXiv preprint arXiv:2603.12269, 2026

HASA: Subnet Allocation for Compute-Constrained Model-Heterogeneous Federated Learning

AH Shahdadian, AM Abdelmoniem, M Taheri, S Nazari, C Herglotz

arXiv preprint arXiv:2606.07621, 2026

Hawx: A hardware-aware framework for fast and scalable approximation of dnns

S Nazari, MS Almasi, M Taheri, A Azarpeyvand, A Mokhtari, A Mahani, ...

2026 Design, Automation & Test in Europe Conference (DATE), 1-7, 2026

Integrating an open-source soft-GPU overlay with RISC-V control and high-bandwidth memory

HGM Hernandez, M Taheri, M Ali, K Shahin, A Syavashi, D Göhringer, ...

Journal of Systems Architecture, 103736, 2026

Mix-and-match pruning: Globally guided layer-wise sparsification of dnns

D Monachan, S Nazari, M Taheri, A Azarpeyvand, M Krstic, M Huebner, ...

arXiv preprint arXiv:2603.20280, 2026

PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators

M Taheri

arXiv preprint arXiv:2603.08724, 2026

Quantization-Aided Cost-Efficient Reliability of CNN Accelerators for Edge AI

M Jenihhin, M Taheri, N Cherezova

Machine Learning Systems: The Role of Hardware Design for Dependable …, 2026

RESQ: A Unified Framework for ReLiability-and SEcurity Enhancement of Quantized Deep Neural Networks

AS Mohammadi, S Nazari, A Azarpeyvand, M Taheri, M Krstic, M Hübner, ...

2026 IEEE 27th Latin American Test Symposium (LATS), 1-4, 2026

Sensitivity-Guided Framework for Pruned and Quantized Reservoir Computing Accelerators

A Jafari, M Taheri, HG Mohammadi, C Herglotz, M Platzner

arXiv preprint arXiv:2603.08737, 2026

SENTRY: Statistical Reliability Analysis of Vision Transformers Under Soft Errors

PK Bhaduri, M Taheri, S Nazari, M Jenihhin, C Herglotz, M Hubner

arXiv preprint arXiv:2606.07620, 2026

SPARQ: Spiking Early-Exit Neural Networks for Energy-Efficient Edge AI

P Patne, M Taheri, A Mahani, M Jenihhin, R Mahani, C Herglotz

arXiv preprint arXiv:2603.14380, 2026

Adaptive Fault Resilience for Early-Exit DNNs

RM Kodamanchili, N Cherezova, M Taheri, M Jenihhin

2025 IEEE International Test Conference in Asia (ITC-Asia), 108-113, 2025

Genie: Genetic algorithm-based reliability assessment methodology for deep neural networks

S Nazari, M Taheri, A Azarpeyvand, M Afsharchi, C Herglotz, M Jenihhin

2025 11th International Conference on Computing and Artificial Intelligence …, 2025

Reliability-Aware Hyperparameter Optimization for ANN-to-SNN Conversion

S Sharifian, M Taheri, V Rashtchi, A Azarpeyvand, C Herglotz, M Jenihhin

WiPiEC Journal-Works in Progress in Embedded Computing Journal 11 (1), 7-7, 2025

Reliability-aware performance optimization of DNN HW accelerators through heterogeneous quantization

S Nazari, M Taheri, A Azarpeyvand, M Afsharchi, C Herglotz, M Jenihhin

2025 IEEE 26th Latin American Test Symposium (LATS), 1-6, 2025

RL-Agent-based Early-Exit DNN Architecture Search Framework

M Taheri, P Patne, N Cherezova, A Mahani, C Herglotz, M Jenihhin

2025 IEEE 28th International Symposium on Design and Diagnostics of …, 2025

SAFFIRA A Framework for Assessing the Reliability of Systolic-Array DNN Accelerators

S Pappalardo, N Bellarmino, B Deveautour, A Bosio, M Taheri, ...

Journal of Circuits, Systems and Computers 34 (18), 2543001, 2025

Shield: Pso-based hardware trojan detection for efficient and low-cost defense

M Hosseini, A Azarpeyvand, M Taheri, T Ghasempouri, M Jenihhin

2025 IEEE 31st International Symposium on On-Line Testing and Robust System …, 2025

A systematic literature review on hardware reliability assessment methods for deep neural networks

MH Ahmadilivani, M Taheri, J Raik, M Daneshtalab, M Jenihhin

ACM Computing Surveys 56 (6), 1-39, 2024

AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators

M Taheri, N Cherezova, S Nazari, A Azarpeyvand, T Ghasempouri, ...

IEEE Transactions on Device and Materials Reliability, 2024

Exploration of activation fault reliability in quantized systolic array-based dnn accelerators

M Taheri, N Cherezova, MS Ansari, M Jenihhin, A Mahani, ...

2024 25th International Symposium on Quality Electronic Design (ISQED), 1-8, 2024

FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs

S Nazari, M Taheri, A Azarpeyvand, M Afsharchi, T Ghasempouri, ...

Authorea Preprints, 2024

Heterogeneous approximation of dnn hw accelerators based on channels vulnerability

N Cherezova, S Pappalardo, M Taheri, MH Ahmadilivani, B Deveautour, ...

2024 IFIP/IEEE 32nd International Conference on Very Large Scale Integration …, 2024

Keynote: Cost-Efficient Reliability for Edge-AI Chips

M Jenihhin, M Taheri, N Cherezova, MH Ahmadilivani, H Selg, A Jutman, ...

2024 IEEE 25th Latin American Test Symposium (LATS), 1-2, 2024

Saffira: a framework for assessing the reliability of systolic-array-based dnn accelerators

M Taheri, M Daneshtalab, J Raik, M Jenihhin, S Pappalardo, P Jimenez, ...

2024 27th International Symposium on Design & Diagnostics of Electronic …, 2024

Special session: Reliability assessment recipes for dnn accelerators

MH Ahmadilivani, A Bosio, B Deveautour, FF Dos Santos, ...

2024 IEEE 42nd VLSI Test Symposium (VTS), 1-11, 2024

Appraiser: Dnn fault resilience analysis employing approximation errors

M Taheri, MH Ahmadilivani, M Jenihhin, M Daneshtalab, J Raik

2023 26th International Symposium on Design and Diagnostics of Electronic …, 2023

Deepaxe: A framework for exploration of approximation and reliability trade-offs in dnn accelerators

M Taheri, M Riazati, MH Ahmadilivani, M Jenihhin, M Daneshtalab, J Raik, ...

2023 24th International Symposium on Quality Electronic Design (ISQED), 1-8, 2023

Deepvigor: Vulnerability value ranges and factors for dnns’ reliability assessment

MH Ahmadilivani, M Taheri, J Raik, M Daneshtalab, M Jenihhin

2023 IEEE European Test Symposium (ETS), 1-6, 2023

Enhancing fault resilience of qnns by selective neuron splitting

MH Ahmadilivani, M Taheri, J Raik, M Daneshtalab, M Jenihhin

arXiv preprint arXiv:2306.09973, 2023

LRDB: LSTM Raw data DNA Base-caller based on long-short term models in an active learning environment

A Rezaei, M Taheri, A Mahani, S Magierowski

arXiv preprint arXiv:2303.08915, 2023

Noise-tolerance gpu-based age estimation using resnet-50

M Taheri, M Taheri, A Hadjahmadi

arXiv preprint arXiv:2305.00848, 2023

Special session: Approximation and fault resiliency of dnn accelerators

MH Ahmadilivani, M Barbareschi, S Barone, A Bosio, M Daneshtalab, ...

2023 IEEE 41st VLSI Test Symposium (VTS), 1-10, 2023

A fault-resistant architecture for aes s-box architecture

M Taheri, S Sheikhpour, MS Ansari, A Mahani

Journal of Applied Research in Electrical Engineering 1 (1), 86-92, 2022

A novel fault-tolerant logic style with self-checking capability

M Taheri, S Sheikhpour, A Mahani, M Jenihhin

2022 IEEE 28th International Symposium on On-Line Testing and Robust System …, 2022

Dnn hardware reliability assessment and enhancement

M Taheri

27th IEEE European Test Symposium (ETS), 2022

A high-performance MEMRISTOR-based Smith-Waterman DNA sequence alignment Using FPNI structure

M Taheri, H Zandevakili, A Mahani

Journal of Applied Research in Electrical Engineering 1 (1), 2021

A Novel 2-D BWA-MEM FPGA Accelerator for Short-Read Mapping of the Whole Human Genome

M Taheri, A Mahani

Journal of Applied Research in Electrical Engineering 1 (2), 203-210, 2021

Development and hardware acceleration of a novel 2-DBWA-MEM DNA sequencing alignment algorithm

M Taheri, A Mahani

DMR-based Technique for Fault Tolerant AES S-box Architecture

M Taheri, S Sheikhpour, MS Ansari, A Mahani

1 st Conference on Applied Research in Electrical Engineering (AREE), 2021

Hardware acceleration of the novel two dimensional Burrows‐Wheeler Aligner algorithm with maximal exact matches seed extension kernel

M Taheri, MS Ansari, S Magierowski, A Mahani

IET Circuits, Devices & Systems 15 (2), 94-103, 2021

Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme

S Sheikhpur, M Taheri, MS Ansari, A Mahani

IET Computers & Digital Techniques 15 (3), 1-14, 2021

28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems-DDECS 2025

H Abdo, J Lappas, M Esmaeilpour, C Weis, N Wehn, AH Hadipour, ...

SPECIAL SECTION ON DFT SYMPOSIUM

D Mateo, X Aragones, E Barajas, SM Domingo, X Gisbert, J Altet, ...